? semiconductor components industries, llc, 2014 august, 2014 ? rev. 10 1 publication order number: mc14043b/d mc14043b, mc14044b cmos msi quad r?s latches the mc14043b and mc14044b quad r?s latches are constructed with mos p?channel and n?channel enhancement mode devices in a single monolithic structure. each latch has an independent q output and set and reset inputs. the q outputs are gated through three?state buffers having a common enable input. the outputs are enabled with a logical ?1? or high on the enable input; a logical ?0? or low disconnects the latch from the q outputs, resulting in an open circuit at the q outputs. features ? double diode input protection ? three?state outputs with common enable ? outputs capable of driving two low?power ttl loads or one low?power schottky ttl load over the rated temperature range ? supply voltage range = 3.0 vdc to 18 vdc ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free and are rohs compliant maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage range ?0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) ?0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 1) 500 mw t a ambient temperature range ?55 to +125 c t stg storage temperature range ?65 to +150 c t l lead temperature (8?second soldering) 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. temperature derating: ?d/dw? packages: ?7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com marking diagrams soic?16 140xxbg awlyww xx = specific device code a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb?free indicator soeiaj?16 mc14043b alywg see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information 1 16 1 16 soic?16 d suffix case 751b soeiaj?16 f suffix case 966
mc14043b, mc14044b http://onsemi.com 2 mc14043b truth table x = don?t care mc14044b sre q high impedance xx0 no change 0 1 1 0 0 1 1 0 1 0 1 1 1 1 1 truth table x = don?t care s r eq high impedance xx0 0 1 0 no change 0 0 1 1 0 1 0 1 1 1 1 1 enable r3 s3 r2 s2 r1 s1 r0 s0 4 3 6 7 12 11 14 15 5 q3 q2 q1 q0 2 9 10 1 enable s3 r3 s2 r2 s1 r1 s0 r0 4 3 6 7 12 11 14 15 5 q3 q2 q1 q0 13 9 10 1 v dd = pin 16 v ss = pin 8 nc = pin 2 v dd = pin 16 v ss = pin 8 nc = pin 13 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 s2 nc s3 r3 v dd q1 q2 r2 s0 r0 q0 q3 v ss r1 s1 e 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 r2 q0 r3 s3 v dd q1 q2 s2 r0 s0 nc q3 v ss s1 r1 e nc = no connection mc14043b mc14044b
mc14043b, mc14044b http://onsemi.com 3 electrical characteristics (voltages referenced to v ss ) characteristic symbo l v dd vdc ? 55 c 25 c 125 c unit min max min typ (note 2) max min max output voltage ?0? leve l v in = v dd or 0 ?1? leve l v in = 0 or v dd v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage ?0? leve l (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) ?1? leve l (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v il 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 vdc v ih 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) (v ol = 0.4 vdc) sin k (v ol = 0.5 vdc) (v ol = 1.5 vdc) i oh 5.0 5.0 10 15 ?3.0 ?0.64 ?1.6 ?4.2 ? ? ? ? ?2.4 ?0.51 ?1.3 ?3.4 ?4.2 ?0.88 ?2.25 ?8.8 ? ? ? ? ?1.7 ?0.36 ?0.9 ?2.4 ? ? ? ? madc i ol 5.0 10 15 0.64 1.6 4.2 ? ? ? 0.51 1.3 3.4 0.88 2.25 8.8 ? ? ? 0.36 0.9 2.4 ? ? ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) i dd 5.0 10 15 ? ? ? 1.0 2.0 4.0 ? ? ? 0.002 0.004 0.006 1.0 2.0 4.0 ? ? ? 30 60 120 adc total supply current (notes 3 & 4) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs all buffers switching) i t 5.0 10 15 i t = (0.58 a/khz) f + i dd i t = (1.15 a/khz) f + i dd i t = (1.73 a/khz) f + i dd adc three?state output leakage current i tl 15 ? 0.1 ? 0.0001 0.1 ? 3.0 adc product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l ? 50) vfk where: i t is in a (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.004.
mc14043b, mc14044b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? (note 5) (c l = 50 pf, t a = 25 c) ??????????????? ??????????????? characteristic ????? ????? ???? ???? ???? ???? ???? ???? (note 6) ???? ???? max ??? ??? ??????????????? ??????????????? ??????????????? ??????????????? output rise time t tlh = (1.35 ns/pf) c l + 32.5 ns t tlh = (0.60 ns/pf) c l + 20 ns t tlh = (0.40 ns/pf) c l + 20 ns ????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??? ??????????????? ??????????????? ??????????????? ??????????????? ????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??? ??????????????? ??????????????? ??????????????? ??????????????? ????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??? ??????????????? ??????????????? ??????????????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??????????????? ??????????????? ??????????????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??????????????? ??????????????? ??????????????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??????????????? ??????????????? ??????????????? ??????????????? ????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??? c. 6. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. ac waveforms mc14043b mc14044b 20 ns 20 ns 90% 10% reset set q t phl t plh 20 ns 20 ns 50% 90% 50% 10% t thl t tlh 90% 50% 10% v dd v ss v dd v ss v oh v ol reset set q 20 ns 20 ns 90% 10% 50% 20 ns 20 ns 90% 10% 50% t tlh t thl 50% 10% 90% t plh t phl v dd v ss v dd v ss v oh v ol
mc14043b, mc14044b http://onsemi.com 5 three?state enable/disable delays set, reset, enable, and switch conditions for 3?state tests test enable s1 s2 q mc14043b mc14044b s r s r t pzh open closed a v dd v ss v ss v dd t pzl closed open b v ss v dd v dd v ss t phz open closed a v dd v ss v ss v dd t plz closed open b v ss v dd v dd v ss enable q a q b 50% t pzh 10% t pzl t phz t plz 10% 90% v dd v ss v dd v ol v oh v ss ordering information device package shipping ? MC14043BDG soic?16 (pb?free) 48 units / rail nlv14043bdg* soic?16 (pb?free) 48 units / rail mc14043bdr2g soic?16 (pb?free) 2500 units / tape & reel nlv14043bdr2g* soic?16 (pb?free) 2500 units / tape & reel mc14043bfelg soeiaj?16 (pb?free) 2000 units / tape & reel mc14044bdg soic?16 (pb?free) 48 units / rail nlv14044bdg* soic?16 (pb?free) 48 units / rail mc14044bdr2g soic?16 (pb?free) 2500 units / tape & reel nlv14044bdr2g* soic?16 (pb?free) 2500 units / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable. to output under test v dd s1 s2 1 k c l 50 pf v ss
mc14043b, mc14044b http://onsemi.com 6 package dimensions soic?16 d suffix case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc14043b, mc14044b http://onsemi.com 7 package dimensions soeiaj?16 f suffix case 966 issue a h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemni fy and hold scillc and its officers, em ployees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc14043b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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